CONTENT PLAN : ATMP- PRIMER WORKSHOP ELCINA-MEITY : 9TH OCTOBER, 2020
Continuing on the knowledge workshop from last week, this session briefly touched the semiconductor industry – and key trends and drivers into the decade of 2020 -and then dived deeper into the Semiconductor Packaging. We covered the history of semiconductor packaging from thru-board packages to surface mounted packages ; from DIP to FO-WLP with the evolving heterogenous integration era via Chiplets shaped by US DARPA led CHIPS program. A brief intro to WBG was given as a prelude to a future WBG semiconductors session.
It is relevant to understand the evolution of ATMP in semiconductors. As the semiconductor die started to add more and more logic and more and more functions, it required more interconnects to the real world. The new generation of semiconductor packaging processes aim at:
- Enabling increasingly more interconnects
- at lower cost/interconnect
- with more functionality
- …and in future with more heterogenous integrations bring multi-chip integration to the System-in-Package in a Lego-like pick-and-place reuse of diverse IP/process enabled devices linked with an evolving common industry interface.
Really appreciate the enthusiastic response from MEITY leadership and the industry…Their warmth has made this effort a pleasure. I am sharing the slides for this session here.
The event recording is shared here.
For reference. I am also sharing the following YouTube videos – one is on the conventional lead-frame, wire-bonded chip assembly and the second briefly mentions the Fan-out process.
Let us start with a brief overview of different packages here:
and then visit a conventional wire-bond chip assembly house here:
and end with Fan-out packaging – a quick brief here:
A final thought for the road.